巴斯多斯3 FPGA上的七段显示的VHDL代码

上次,我写了一个完整的FPGA教程,用于如何控制Basys 3 FPGA上的4位7段显示。一种 用于在7段显示器上显示计数4位数十进制数的完整Verilog代码 was also provided.

VHDL.项目 将呈现完整的 VHDL. 七段显示的代码 巴斯多斯3 FPGA。这 七段显示 在Basys 3 FPGA将用于显示每1秒钟计算的4位十六进制数。 

巴斯多斯3 FPGA上的七段显示的VHDL代码

首先,真相表 BCD到Basys 3 FPGA上的7段显示解码器 is as follows: 
BCD到Basys 3 FPGA的7段显示的真实表

VHDL.码 为了 BCD到7段显示解码器:

-- fpga4student: FPGA. projects, Verilog projects, VHDL.项目
-- Example VHDL code for BCD to Basys 3 FPGA上的七段显示
process(LED_BCD)
begin
    case LED_BCD is
    when "0000" => LED_out <= "0000001"; -- "0"     
    when "0001.." => LED_out <= "1001111"; -- "1" 
    when "0010" => LED_out <= "0010010"; -- "2" 
    when "0011" => LED_out <= "0000110"; -- "3" 
    when "0100" => LED_out <= "1001100"; -- "4" 
    when "0101" => LED_out <= "0100100"; -- "5" 
    when "0110" => LED_out <= "0100000"; -- "6" 
    when "0111" => LED_out <= "0001..111"; -- "7" 
    when "1000" => LED_out <= "0000000"; -- "8"     
    when "1001" => LED_out <= "0000100"; -- "9" 
    when "1010" => LED_out <= "0000010"; -- a
    when "1011" => LED_out <= "1100000"; -- b
    when "1100" => LED_out <= "0110001"; -- C
    when "1101" => LED_out <= "1000010"; -- d
    when "1110" => LED_out <= "0110000"; -- E
    when "1111" => LED_out <= "0111000"; -- F
    end case;
end process;

接下来,我提到的 教程,必须使用七段显示控制器来控制Basys 3 FPGA上的4位七段显示。

以下是刷新Basys 3 FPGA上的4位七段显示器的时序图:
4位七段显示的时序图
刷新 4位数七段显示所需的速率为1ms至16ms。让我们选择10.5ms作为刷新期。以下是一个例子 VHDL.码 用于在Basys 3 FPGA上为4位七段显示器创建刷新率和阳极信号:
-- 7-segment display controller
-- generate refresh period of 10.5ms
process(clock_100Mhz,reset)
begin 
    if(reset='1') then
        refresh_counter <= (others => '0');
    elsif(rising_edge(clock_100Mhz)) then
        refresh_counter <= refresh_counter + 1;
    end if;
end process;
 LED_activating_counter <= refresh_counter(19 downto 18);
-- 4-to-1 MUX to generate anode activating signals for 4 LEDs 
process(LED_activating_counter)
begin
    case LED_activating_counter is
    when "00" =>
        Anode_Activate <= "0111"; 
        -- activate LED1 and Deactivate LED2, LED3, LED4
        LED_BCD <= displayed_number(15 downto 12);
        -- the first hex digit of the 16-bit number
    when "01" =>
        Anode_Activate <= "1011"; 
        -- activate LED2 and Deactivate LED1, LED3, LED4
        LED_BCD <= displayed_number(11 downto 8);
        -- the second hex digit of the 16-bit number
    when "10" =>
        Anode_Activate <= "1101"; 
        -- activate LED3 and Deactivate LED2, LED1, LED4
        LED_BCD <= displayed_number(7 downto 4);
        -- the third hex digit of the 16-bit number
    when "11" =>
        Anode_Activate <= "1110"; 
        -- activate LED4 and Deactivate LED2, LED3, LED1
        LED_BCD <= displayed_number(3 downto 0);
        -- the fourth hex digit of the 16-bit number    
    end case;
end process;

现在,让我们使用它来显示计数的十六进制数 Basys 3 FPGA上的4位数七段显示器 .

Bays 3 FPGA上的七段显示的VHDL代码:

-- fpga4student.com: FPGA. projects, Verilog projects, VHDL.项目
-- VHDL code for Basys 3 FPGA上的七段显示
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity seven_segment_display_VHDL is
    Port ( clock_100Mhz : in STD_LOGIC;-- 100Mhz clock on Basys 3 FPGA board
           reset : in STD_LOGIC; -- reset
           Anode_Activate : out STD_LOGIC_VECTOR (3 downto 0);-- 4 Anode signals
           LED_out : out STD_LOGIC_VECTOR (6 downto 0));-- Cathode patterns of 7-segment display
end seven_segment_display_VHDL;

architecture Behavioral of seven_segment_display_VHDL is
signal one_second_counter: STD_LOGIC_VECTOR (27 downto 0);
-- counter for generating 1-second clock enable
signal one_second_enable: std_logic;
-- one second enable for counting numbers
signal displayed_number: STD_LOGIC_VECTOR (15 downto 0);
-- counting decimal number to be displayed on 4-digit 7-segment display
signal LED_BCD: STD_LOGIC_VECTOR (3 downto 0);
signal refresh_counter: STD_LOGIC_VECTOR (19 downto 0);
-- creating 10.5ms refresh period
signal LED_activating_counter: std_logic_vector(1 downto 0);
-- the other 2-bit for creating 4 LED-activating signals
-- count         0    ->  1  ->  2  ->  3
-- activates    LED1    LED2   LED3   LED4
-- and repeat
begin
-- VHDL code for BCD to 7-segment decoder
-- Cathode patterns of the 7-segment LED display 
process(LED_BCD)
begin
    case LED_BCD is
    when "0000" => LED_out <= "0000001"; -- "0"     
    when "0001.." => LED_out <= "1001111"; -- "1" 
    when "0010" => LED_out <= "0010010"; -- "2" 
    when "0011" => LED_out <= "0000110"; -- "3" 
    when "0100" => LED_out <= "1001100"; -- "4" 
    when "0101" => LED_out <= "0100100"; -- "5" 
    when "0110" => LED_out <= "0100000"; -- "6" 
    when "0111" => LED_out <= "0001..111"; -- "7" 
    when "1000" => LED_out <= "0000000"; -- "8"     
    when "1001" => LED_out <= "0000100"; -- "9" 
    when "1010" => LED_out <= "0000010"; -- a
    when "1011" => LED_out <= "1100000"; -- b
    when "1100" => LED_out <= "0110001"; -- C
    when "1101" => LED_out <= "1000010"; -- d
    when "1110" => LED_out <= "0110000"; -- E
    when "1111" => LED_out <= "0111000"; -- F
    end case;
end process;
-- 7-segment display controller
-- generate refresh period of 10.5ms
process(clock_100Mhz,reset)
begin 
    if(reset='1') then
        refresh_counter <= (others => '0');
    elsif(rising_edge(clock_100Mhz)) then
        refresh_counter <= refresh_counter + 1;
    end if;
end process;
 LED_activating_counter <= refresh_counter(19 downto 18);
-- 4-to-1 MUX to generate anode activating signals for 4 LEDs 
process(LED_activating_counter)
begin
    case LED_activating_counter is
    when "00" =>
        Anode_Activate <= "0111"; 
        -- activate LED1 and Deactivate LED2, LED3, LED4
        LED_BCD <= displayed_number(15 downto 12);
        -- the first hex digit of the 16-bit number
    when "01" =>
        Anode_Activate <= "1011"; 
        -- activate LED2 and Deactivate LED1, LED3, LED4
        LED_BCD <= displayed_number(11 downto 8);
        -- the second hex digit of the 16-bit number
    when "10" =>
        Anode_Activate <= "1101"; 
        -- activate LED3 and Deactivate LED2, LED1, LED4
        LED_BCD <= displayed_number(7 downto 4);
        -- the third hex digit of the 16-bit number
    when "11" =>
        Anode_Activate <= "1110"; 
        -- activate LED4 and Deactivate LED2, LED3, LED1
        LED_BCD <= displayed_number(3 downto 0);
        -- the fourth hex digit of the 16-bit number    
    end case;
end process;
-- Counting the number to be displayed on 4-digit 7-segment Display 
-- on Basys 3 FPGA board
process(clock_100Mhz, reset)
begin
        if(reset='1') then
            one_second_counter <= (others => '0');
        elsif(rising_edge(clock_100Mhz)) then
            if(one_second_counter>=x"5F5E0FF") then
                one_second_counter <= (others => '0');
            else
                one_second_counter <= one_second_counter + "0000001";
            end if;
        end if;
end process;
one_second_enable <= '1' when one_second_counter=x"5F5E0FF" else '0';
process(clock_100Mhz, reset)
begin
        if(reset='1') then
            displayed_number <= (others => '0');
        elsif(rising_edge(clock_100Mhz)) then
             if(one_second_enable='1') then
                displayed_number <= displayed_number + x"0001..";
             end if;
        end if;
end process;
end Behavioral;

PIN分配约束文件在Basys 3 FPGA上的4位七段显示:

# Clock signal
set_property PACKAGE_PIN W5 [get_ports clock_100Mhz]       
 set_property IOSTANDARD LVCMOS33 [get_ports clock_100Mhz]
set_property PACKAGE_PIN R2 [get_ports reset]     
        set_property IOSTANDARD LVCMOS33 [get_ports reset]
#seven-segment LED display
        set_property PACKAGE_PIN W7 [get_ports {LED_out[6]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[6]}]
        set_property PACKAGE_PIN W6 [get_ports {LED_out[5]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[5]}]
        set_property PACKAGE_PIN U8 [get_ports {LED_out[4]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[4]}]
        set_property PACKAGE_PIN V8 [get_ports {LED_out[3]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[3]}]
        set_property PACKAGE_PIN U5 [get_ports {LED_out[2]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[2]}]
        set_property PACKAGE_PIN V5 [get_ports {LED_out[1]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[1]}]
        set_property PACKAGE_PIN U7 [get_ports {LED_out[0]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {LED_out[0]}]
        set_property PACKAGE_PIN U2 [get_ports {Anode_Activate[0]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[0]}]
        set_property PACKAGE_PIN U4 [get_ports {Anode_Activate[1]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[1]}]
        set_property PACKAGE_PIN V4 [get_ports {Anode_Activate[2]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[2]}]
        set_property PACKAGE_PIN W4 [get_ports {Anode_Activate[3]}]                    
            set_property IOSTANDARD LVCMOS33 [get_ports {Anode_Activate[3]}]
使用 VHDL.源 文件和约束文件,在Vivado中创建一个项目,并在Basys 3上运行VHDL代码 FPGA.。下面是演示视频 巴斯多斯3 FPGA上的七段显示:
FPGA. Verilog VHDL课程

11评论:

  1. 如何为这个项目制作一个测试台?任何帮助,将不胜感激。

    回复删除
    答案
    1. 只需在TestBench中生成时钟并重置,然后观察模拟波形。那's it.

      删除
    2. 不,不起作用。只有你看到的东西是时钟和重置。当您添加其他对象时,它们的值是"U" or "XXXXX"
      请上传您的测试台。

      删除
  2. 答案
    1. 只需从spows_number更改<= spains_number + x"0001"to sames_number.<= spains_number - x"0001";

      删除
  3. 你好,我想知道如何改变频率和刷新率吗?
    例如,如1秒钟到100Hz,10.5ms略微更快。
    谢谢。

    回复删除
  4. 如何使用结构模型编写相同的代码?

    回复删除
  5. 请告诉我如何使用结构建模写相同的代码

    回复删除

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