交通信号灯控制器的VHDL代码

A 甚高密度脂蛋白代码 为一个 交通灯控制器现场可编程门阵列 被呈现。 甚高密度脂蛋白中的交通信号灯控制器用于高速公路和农场之间的交叉路口。 

有一个 传感器 在农场路侧检查是否在农场路上有任何车辆。如果在农场道路上检测到车辆,则高速公路上的交通信号灯将变为黄色,然后变为红色,以便来自农场道路的车辆可以越过高速公路。否则,高速公路上的交通信号灯始终为绿色,而农场路的交通信号灯始终为红色。黄色灯的时间段为3秒,红色灯的时间段为10秒。 

交通信号灯控制器的VHDL代码

甚高密度脂蛋白 交通信号灯控制器代码:

-- fpga4student.com 现场可编程门阵列 projects, 甚高密度脂蛋白项目, Verilog projects
-- 甚高密度脂蛋白 project: 甚高密度脂蛋白代码 for 交通灯控制器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;  
-- Traffic ligh system 为一个 intersection between highway and farm way 
-- 有一个 传感器 上  the farm way side, when there are vehicles, 
-- Traffic light turns to YELLOW, then GREEN to let the vehicles cross the highway 
-- Otherwise, always green light 上  Highway and Red light 上  farm way 
entity traffic_light_controller is
 port ( 传感器  : in STD_LOGIC; -- Sensor 
        clk  : in STD_LOGIC; -- clock 
        rst_n: in STD_LOGIC; -- reset active low 
        light_highway  : out STD_LOGIC_VECTOR(2 downto 0); -- light outputs of high way
     light_farm:    out STD_LOGIC_VECTOR(2 downto 0)-- light outputs of farm way
     --RED_YELLOW_GREEN 
   );
end traffic_light_controller;
architecture traffic_light of traffic_light_controller is
signal counter_1s: std_logic_vector(27 downto 0):= x"0000000";
signal delay_count:std_logic_vector(3 downto 0):= x"0";
signal delay_10s, delay_3s_F,delay_3s_H, RED_LIGHT_ENABLE, YELLOW_LIGHT1_ENABLE,YELLOW_LIGHT2_ENABLE: std_logic:='0';
signal clk_1s_enable: std_logic; -- 1s clock enable 
type FSM_States is (HGRE_FRED, HYEL_FRED, HRED_FGRE, HRED_FYEL);
-- HGRE_FRED : Highway green and farm red
-- HYEL_FRED : Highway yellow and farm red
-- HRED_FGRE : Highway red and farm green
-- HRED_FYEL : Highway red and farm yellow
signal current_state, next_state: FSM_States;
begin
-- next state FSM sequential logic 
process(clk,rst_n) 
begin
if(rst_n='0') then
 current_state <= HGRE_FRED;
elsif(rising_edge(clk)) then 
 current_state <= next_state; 
end if; 
end process;
-- FSM combinational logic 
process(current_state,sensor,delay_3s_F,delay_3s_H,delay_10s)
begin
case current_state is 
when HGRE_FRED => -- When Green light 上  Highway and Red light 上  Farm way
 RED_LIGHT_ENABLE <= '0';-- disable RED light delay counting
 YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
 YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
 light_highway <= "001"; -- Green light 上  Highway
 light_farm <= "100"; -- Red light 上  Farm way 
 if(sensor = '1') then -- if vehicle is detected 上  farm way by 传感器s
  next_state <= HYEL_FRED; 
  -- High way turns to Yellow light 
 else 
  next_state <= HGRE_FRED; 
  -- Otherwise, remains GREEN ON highway and RED 上  Farm way
 end if;
when HYEL_FRED => -- When Yellow light 上  Highway and Red light 上  Farm way
 light_highway <= "010";-- Yellow light 上  Highway
 light_farm <= "100";-- Red light 上  Farm way 
 RED_LIGHT_ENABLE <= '0';-- disable RED light delay counting
 YELLOW_LIGHT1_ENABLE <= '1';-- enable YELLOW light Highway delay counting
 YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
 if(delay_3s_H='1') then 
 -- if Yellow light delay counts to 3s, 
 -- turn Highway to RED, 
 -- Farm way to green light 
  next_state <= HRED_FGRE; 
 else 
  next_state <= HYEL_FRED; 
  -- Remains Yellow 上  highway and Red 上  Farm way 
  -- if Yellow light not yet in 3s 
 end if;
when HRED_FGRE => 
 light_highway <= "100";-- RED light 上  Highway 
 light_farm <= "001";-- GREEN light 上  Farm way 
 RED_LIGHT_ENABLE <= '1';-- enable RED light delay counting
 YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
 YELLOW_LIGHT2_ENABLE <= '0';-- disable YELLOW light Farmway delay counting
 if(delay_10s='1') then
 -- if RED light 上  highway is 10s, Farm way turns to Yellow
  next_state <= HRED_FYEL;
 else 
  next_state <= HRED_FGRE; 
  -- Remains if delay counts for RED light 上  highway not enough 10s 
 end if;
when HRED_FYEL =>
 light_highway <= "100";-- RED light 上  Highway 
 light_farm <= "010";-- Yellow light 上  Farm way 
 RED_LIGHT_ENABLE <= '0'; -- disable RED light delay counting
 YELLOW_LIGHT1_ENABLE <= '0';-- disable YELLOW light Highway delay counting
 YELLOW_LIGHT2_ENABLE <= '1';-- enable YELLOW light Farmway delay counting
 if(delay_3s_F='1') then 
 -- if delay for Yellow light is 3s,
 -- turn highway to GREEN light
 -- Farm way to RED Light
 next_state <= HGRE_FRED;
 else 
 next_state <= HRED_FYEL;
 -- if not enough 3s, remain the same state 
 end if;
when others => next_state <= HGRE_FRED; -- Green 上  highway, red 上  farm way 
end case;
end process;
-- Delay counts for Yellow and RED light  
process(clk)
begin
if(rising_edge(clk)) then 
if(clk_1s_enable='1') then
 if(RED_LIGHT_ENABLE='1' or YELLOW_LIGHT1_ENABLE='1' or YELLOW_LIGHT2_ENABLE='1') then
  delay_count <= delay_count + x"1";
  if((delay_count = x"9") and RED_LIGHT_ENABLE ='1') then 
   delay_10s <= '1';
   delay_3s_H <= '0';
   delay_3s_F <= '0';
   delay_count <= x"0";
  elsif((delay_count = x"2") and YELLOW_LIGHT1_ENABLE= '1') then
   delay_10s <= '0';
   delay_3s_H <= '1';
   delay_3s_F <= '0';
   delay_count <= x"0";
  elsif((delay_count = x"2") and YELLOW_LIGHT2_ENABLE= '1') then
   delay_10s <= '0';
   delay_3s_H <= '0';
   delay_3s_F <= '1';
   delay_count <= x"0";
  else
   delay_10s <= '0';
   delay_3s_H <= '0';
   delay_3s_F <= '0';
  end if;
 end if;
 end if;
end if;
end process;
-- create delay 1s
process(clk)
begin
if(rising_edge(clk)) then 
 counter_1s <= counter_1s + x"0000001";
 if(counter_1s >= x"0000003") then -- x"0004" is for simulation
 -- change to x"2FAF080" for 50 MHz clock running real 现场可编程门阵列
  counter_1s <= x"0000000";
 end if;
end if;
end process;
clk_1s_enable <= '1' when counter_1s = x"0003" else '0'; -- x"0002" is for simulation
-- x"2FAF080" for 50Mhz clock 上  现场可编程门阵列
end traffic_light;

交通信号灯控制器的VHDL Testbench代码:

-- fpga4student.com 现场可编程门阵列 projects, 甚高密度脂蛋白项目, Verilog projects
-- 甚高密度脂蛋白 project: 甚高密度脂蛋白代码 for 交通灯控制器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Testbench 甚高密度脂蛋白代码 for 交通灯控制器 
ENTITY tb_traffic_light_controller IS
END tb_traffic_light_controller;

ARCHITECTURE behavior OF tb_traffic_light_controller IS 
    -- Component Declaration for the 交通灯控制器 
    COMPONENT traffic_light_controller
    PORT(
         传感器 : IN  std_logic;
         clk : IN  std_logic;
         rst_n : IN  std_logic;
         light_highway : OUT  std_logic_vector(2 downto 0);
         light_farm : OUT  std_logic_vector(2 downto 0)
        );
    END COMPONENT;
   signal 传感器 : std_logic := '0';
   signal clk : std_logic := '0';
   signal rst_n : std_logic := '0';
  --Outputs
   signal light_highway : std_logic_vector(2 downto 0);
   signal light_farm : std_logic_vector(2 downto 0);
   constant clk_period : time := 10 ns;
BEGIN
 -- Instantiate the 交通灯控制器 
   trafficlightcontroller : traffic_light_controller PORT MAP (
          传感器 => 传感器,
          clk => clk,
          rst_n => rst_n,
          light_highway => light_highway,
          light_farm => light_farm
        );
   -- Clock process definitions
   clk_process :process
   begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
   end process;
   stim_proc: process
   begin    
  rst_n <= '0';
  传感器 <= '0';
      wait for clk_period*10;
  rst_n <= '1';
  wait for clk_period*20;
  传感器 <= '1';
  wait for clk_period*100;
  传感器 <= '0';
      wait;
   end process;

END;

甚高密度脂蛋白中交通信号灯控制器的仿真波形:

交通信号灯控制器的VHDL代码
交通信号灯控制器的Verilog代码: 这里
现场可编程门阵列 Verilog 甚高密度脂蛋白课程

21条评论:

  1. 你好。我已经使用50 MHZ时钟(Y1)尝试过此代码,但无法'工作。你能帮我解决这个问题吗?非常感谢

    回复删除
    回覆
    1. 您是否合成了代码?合成后该工具说了什么?时间到了吗?

      删除
  2. 您好,我遇到了同样的问题。您能帮我解决这个问题吗

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    1. 使用50Mhz时钟时,是否按照代码中所述更改了时钟除数?

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  3. 您好,先生,您能帮我从这个程序中显示七段延迟吗?

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    1. 这里:
      http://www.hzgifts.cn/2017/09/seven-segment-led-display-controller-basys3-fpga.html
      http://www.hzgifts.cn/2017/09/vhdl-code-for-seven-segment-display.html

      删除
  4. 嗨!如何使用segment7在vhdl代码中显示红色和绿色指示灯的剩余时间?你能帮我吗?

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    回覆
    1. 这里:
      http://www.hzgifts.cn/2017/09/seven-segment-led-display-controller-basys3-fpga.html
      http://www.hzgifts.cn/2017/09/vhdl-code-for-seven-segment-display.html

      删除
  5. 你好,

    不使用它怎么能写同样的代码"after" , "wait for" or state machines?

    我想我可以使用计数器使用流程来做到这一点,但是我不知道't know how...

    回复删除
  6. 你好,
    你怎么能不使用而编写相同的代码"after" , "wait for", or state machines?

    我想我可以使用计数器,使用流程,但是我不知道't know how...

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  7. 您在这里使用哪种类型的fpga?

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  8. 这里使用哪种类型的fpga?

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  9. 这个项目是2way还是4way?

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  10. 请!我需要你的帮助。您可以上传Basys 3的引脚分配约束文件吗?

    回复删除
  11. 我是VHDL编码的新手,但是
    您只能使用一个yellow_light_enable吗?
    而不是使用两个做相同的事情?

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    回覆
    1. it'由您决定。只要模拟有效,就可以做任何您想做的事情。

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  12. 先生,您好,请您详细说明一下这段代码

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  13. 我们如何将这些代码放入FPGA硬件中?

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  14. 嗨,创建这个项目需要什么电子材料?谢谢!

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