VHDL.中的加密协处理器设计

在这方面 VHDL.项目,完整 协商师 对于加密应用程序在VHDL中设计和实现。 

如上所述 Verilog / VHDL. 项目,协处理器提供了用于安全性特定的标准说明和专用功能单位。协处理器的设计和实现 VHDL.,但ALU单位中的N位加法器在Verilog中实施。 

协处理器的框图如下:
VHDL.中的加密协处理器设计

首先,让我们实现协处理器的组合逻辑单元。以下是组合逻辑单元的框图:
VHDL.中的加密协处理器设计

在先前的帖子中发布了组合逻辑单元的主要模块,如ALU,Shifting单元和非线性查找操作:

alu设计在vhdl

vhdl的变速器设计

VHDL.中的非线性查找实现

协处理器的指令集架构如下:

0.补充:ABUS + BBUS - > RESULT
1.亚:ABUS - BBUS - > RESULT
2.和:ab& BBUS -> RESULT
3.或:ABUS | BBUS - > RESULT
4. xor:ab ab ^ bbus - > RESULT
5.不是:〜艾滋病 - > RESULT
6. MOV:ABUS - > RESULT

7. NOP:没有操作
8. ROR8:结果<= ShiftInput(7 downto 0)&ShiftInput(15下降到8);
9. ROR4:结果<= ShiftInput(3 Downto 0)&ShiftInput(15下降4);
10. SLL8:结果<= ShiftInput(7 downto 0) & "00000000";
11. LUT:结果<=查找表的输出实现

Coprocessor组合逻辑单元的VHDL代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: Cryptographic coprocessor Design in VHDL
-- VHDL code for Combinational Logic unit of the coprocessor
entity structural_VHDL is
port ( A_BUS: in std_logic_vector(15 downto 0);
   B_BUS: in std_logic_vector(15 downto 0);
   CTRL: in std_logic_vector(3 downto 0);
   RESULT: out std_logic_vector(15 downto 0)
  );
end structural_VHDL;

architecture Behavioral of structural_VHDL is
component non_linear_lookup is
port (  LUTIN: in std_logic_vector(7 downto 0);
   LUTOUT: out std_logic_vector(7 downto 0)
 );
end component non_linear_lookup;
component shifter is
  generic ( N: integer:=16
  );
    Port ( SHIFTINPUT : in  STD_LOGIC_VECTOR(N-1 downto 0);
   SHIFT_Ctrl : in  STD_LOGIC_VECTOR(3 downto 0); 
   SHIFTOUT: out  STD_LOGIC_VECTOR(N-1 downto 0)
  );
end component shifter;
component ALU is
 port (
   ABUS: in std_logic_vector(15 downto 0);
   BBUS: in std_logic_vector(15 downto 0);
   ALUctrl: in std_logic_vector(3 downto 0);
   ALUOUT: out std_logic_vector(15 downto 0)
   );
end component ALU;
signal tmp_out1,tmp_out2,tmp_out3: std_logic_vector(15 downto 0);
signal lut_out: std_logic_vector(7 downto 0);
begin
-------------
-- ALU Unit--
-------------
ALU_unit: ALU port map( ABUS => A_BUS, BBUS => B_BUS,ALUctrl => CTRL,ALUOUT => tmp_out1); 
-----------------
-- Shifter Unit--
-----------------
shifter_unit: shifter generic map ( N => 16) -- shifter
 port map( SHIFTINPUT => B_BUS, SHIFT_Ctrl => CTRL,SHIFTOUT => tmp_out2 ); 
-------------------------------------
-- Non-linear Lookup Operation Unit--
-------------------------------------
non_linear_lookup_unit: non_linear_lookup
 port map( LUTIN => A_BUS(7 downto 0), LUTOUT => lut_out);
 tmp_out3 <= A_BUS(15 downto 8) & lut_out;

-----------------------
-- Control Logic Unit--
-----------------------
control_logic: process(CTRL,tmp_out1,tmp_out3,tmp_out2) begin
  case(CTRL(3 downto 3)) is
  when "0" => 
    RESULT <= tmp_out1;
  when others => 
    case(CTRL(1 downto 0)) is
    when "11" =>
     RESULT <= tmp_out3;
    when others =>
     RESULT <= tmp_out2;
    end case;
  end case;
 end process control_logic;
 
end Behavioral;

注册文件的VHDL代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL.项目
-- VHDL project: Cryptographic coprocessor Design in VHDL
-- VHDL code for 16x16 bit Register File( Read/Write Synchronous)
entity register_file is
port ( clock: in std_logic; -- clock 
   reset: in std_logic; -- reset
   RdWEn: in std_logic; -- write enable signal
   RES : in std_logic_vector(15 downto 0); -- write value
   Ra,Rb,Rd: in std_logic_vector(3 downto 0); -- selected value of Registers Ra, Rb, Rd
   SRCa,SRCb: out std_logic_vector(15 downto 0) -- read value
  );
end register_file;

architecture Behavioral of register_file is

type mem_type is array(0 to 15) of std_logic_vector(15 downto 0);
signal REG_FILE: mem_type :=( -- memory initialization
  0 => x"0001", 
  1 => x"c505",
  2 => x"3c07",
  3 => x"4d05",
  4 => x"1186",
  5 => x"f407",
  6 => x"1086",
  7 => x"4706",
  8 => x"6808",
  9 => x"baa0",
  10 => x"c902",
  11 => x"100b",
  12 => x"c000",
  13 => x"c902",
  14 => x"100b",
  15 => x"B000",
  others => (others => '0')
  );
begin
----------------------------------
-- Write Operation (Synchronous)--
----------------------------------
write_operation: process(clock) 
begin
if(rising_edge(clock)) then
 if(RdWEn='1') then -- Write when RdWEn = '1'
  REG_FILE(to_integer(unsigned(Rd))) <= RES;
 end if;
end if;
end process;
----------------------------------
-- Read Operation (Synchronous)--
----------------------------------
read_operation: process(clock)
begin
if(rising_edge(clock)) then
 if(reset='1') then
  SRCa <= x"0000";
  SRCb <= x"0000";
 else
  SRCa <= REG_FILE(to_integer(unsigned(Ra)));
  SRCb <= REG_FILE(to_integer(unsigned(Rb)));
 end if;
end if;
end process;
end Behavioral;

完整的协作者的VHDL代码:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: Cryptographic coprocessor Design in VHDL
-- Complete Processor in VHDL
entity Co_Processor is
port ( 
   clock, reset: in std_logic; -- clock and reset
   CTRL: in std_logic_vector(3 downto 0); -- Control Opcode
   Ra, Rb, Rd: in std_logic_vector(3 downto 0) -- Ra, Rb: Source Registers, Rd: Destination Register
   
  );
end Co_Processor;

architecture Behavioral of Co_Processor is
-- Register file in VHDL 
component register_file is
port ( clock: in std_logic;
   reset: in std_logic;
   RdWEn: in std_logic; 
   RES : in std_logic_vector(15 downto 0); -- write value
   Ra,Rb,Rd: in std_logic_vector(3 downto 0); -- selected value of Registers Ra, Rb, Rd
   SRCa,SRCb: out std_logic_vector(15 downto 0) -- read value
  );
end component register_file;
-- Combinational logic in VHDL
component structural_VHDL is
port ( A_BUS: in std_logic_vector(15 downto 0);
   B_BUS: in std_logic_vector(15 downto 0);
   CTRL: in std_logic_vector(3 downto 0);
   RESULT: out std_logic_vector(15 downto 0)
  );
end component structural_VHDL;
signal Write_Enable: std_logic;
signal read_data1,read_data2,write_data:std_logic_vector(15 downto 0);
signal ctrl_tmp: std_logic_vector(3 downto 0);
signal Rd_tmp: std_logic_vector(3 downto 0);
begin
-- 16x 16-bit Register file in VHDL 
Register_file_16x16: register_file port map( clock=> clock, reset => reset  ,
            RdWEn => Write_Enable, RES => write_data, Ra => Ra, Rb => Rb, Rd => Rd_tmp,
            SRCa => read_data1, SRCb => read_data2);
-- Combinational logic in VHDL
Combinational_logic: structural_VHDL port map( A_BUS=>read_data1, B_BUS => read_data2, CTRL => ctrl_tmp,
             RESULT => write_data);
--- input register VHDL
process(clock,reset) begin
if(rising_edge(clock)) then
 if(reset = '1') then
  ctrl_tmp <= x"0";
  Rd_tmp <= x"0";
 else
  Rd_tmp <= Rd;
  ctrl_tmp <= CTRL;
  if(ctrl_tmp = "0111") then -- NOP Instruction -- DO not allow to write to the Register file
   Write_Enable <= '0';
  else
   Write_Enable <= '1';   
  end if;
 end if;
end if;

end process;
                        
end Behavioral;

VHDL. Cryptographic Coprocessor的测试码:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: Cryptographic coprocessor Design in VHDL
-- VHDL Testbench Code to verify the coprocessor
 
ENTITY test_program IS
END test_program;
 
ARCHITECTURE behavior OF test_program IS 
    -- Component Declaration for the coprocessor
    COMPONENT Co_Processor
    PORT(
         clock : IN  std_logic;
         reset : IN  std_logic;
         CTRL : IN  std_logic_vector(3 downto 0);
         Ra : IN  std_logic_vector(3 downto 0);
         Rb : IN  std_logic_vector(3 downto 0);
         Rd : IN  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   --Inputs
   signal clock : std_logic := '0';
   signal reset : std_logic := '0';
   signal CTRL : std_logic_vector(3 downto 0) := (others => '0');
   signal Ra : std_logic_vector(3 downto 0) := (others => '0');
   signal Rb : std_logic_vector(3 downto 0) := (others => '0');
   signal Rd : std_logic_vector(3 downto 0) := (others => '0');
   -- Clock period definitions
   constant clock_period : time := 20 ns;
BEGIN
 -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
 -- VHDL project: Cryptographic coprocessor Design in VHDL
 -- Instantiate the coprocessor
   uut: Co_Processor PORT MAP (
          clock => clock,
          reset => reset,
          CTRL => CTRL,
          Ra => Ra,
          Rb => Rb,
          Rd => Rd
        );
   -- Clock process definitions
   clock_process :process
   begin
  clock <= '0';
  wait for clock_period/2;
  clock <= '1';
  wait for clock_period/2;
   end process;
   stim_proc: process
   begin  
      -- hold reset state for 100 ns.
  reset <= '1';
  Ra <= "0000";
  Rb <= "0000";
  Rd <= "0000";
  CTRL <= "0111";
      wait for 100 ns; 
  reset <= '0';--- ADD R5,R4, R12
  Ra <= "0101";
  Rb <= "0100";
  Rd <= "1100";
  CTRL <= "0000";
      wait for clock_period;
  Ra <= "0001"; --- XOR R1,R8,R7
  Rb <= "1000";
  Rd <= "0111";
  CTRL <= "0100";
      wait for clock_period;
  Ra <= "0001"; --- ROR4 R12,R0
  Rb <= "1100";
  Rd <= "0000";
  CTRL <= "1001";
      wait for clock_period;    
  Ra <= "0001"; --- SLL8 R9,R3
  Rb <= "1001";
  Rd <= "0011";
  CTRL <= "1010";
      wait for clock_period;
  Ra <= "0000"; --- ADD R0,R7,R10
  Rb <= "0111";
  Rd <= "1010";
  CTRL <= "0000";
      wait for clock_period;
  Ra <= "0111"; --- SUB R7,R3,R12
  Rb <= "0011";
  Rd <= "1100";
  CTRL <= "0001";
  --- NOP
 -- CTRL <= "0111";
      wait for clock_period;
  Ra <= "1100"; --- AND R12,R10,R9
  Rb <= "1010";
  Rd <= "1001";
  CTRL <= "0010";
  --- NOP
 -- CTRL <= "0111";
      wait for clock_period;
  Ra <= "1001"; --- LUT R9,R2
  Rb <= "1010";
  Rd <= "0010";
  CTRL <= "1011";  
      wait;
   end process;

END;

Cryptographic Coprocessor的模拟波形:

使用VHDL TestBench完全验证VHDL中的加密协处理器。您可以尝试许多不同的测试程序来查看协处理器的工作原理。除了观察模拟波形外,请查看寄存器文件的内存内容,以查看指令如何影响寄存器文件。

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