带testbench的计数器的Verilog代码

在这个项目中 Verilogcode 对于 柜台试验台 将显示包括递增计数器,递减计数器,递减计数器和随机计数器。

带testbench的计数器的Verilog代码

Verilogcode 对于 up counter:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 up counter
module up_counter(input clk, reset, output[3:0] counter
    );
reg [3:0] counter_up;

// up counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_up <= 4'd0;
else
 counter_up <= counter_up + 4'd1;
end 
assign counter = counter_up;
endmodule

计数器的Verilog测试平台代码:


// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 up counter 与 试验台
// Testbench Verilogcode 对于 up counter
module upcounter_testbench();
reg clk, reset;
wire [3:0] counter;

up_counter dut(clk, reset, counter);
initial begin 
clk=0;
对于ever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule 

递增计数器的仿真波形:

Verilogcode 对于 up counter

Verilogcode 对于 down counter:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 down counter
module down_counter(input clk, reset, output [3:0] counter
    );
reg [3:0] counter_down;

// down counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_down <= 4'hf;
else
 counter_down <= counter_down - 4'd1;
end 
assign counter = counter_down;
endmodule

计数器的Verilog测试平台代码:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 down counter 与 试验台
// Testbench Verilogcode 对于 down counter
module downcounter_testbench();
reg clk, reset;
wire [3:0] counter;

down_counter dut(clk, reset, counter);
initial begin 
clk=0;
对于ever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule 

递减计数器的仿真波形:

Verilogcode 对于 down counter

Verilog 上下计数器的代码:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 up-down counter
module up_down_counter(input clk, reset,up_down, output[3:0]  counter
    );
reg [3:0] counter_up_down;

// down counter
always @(posedge clk or posedge reset)
begin
if(reset)
 counter_up_down <= 4'h0;
else if(~up_down)
 counter_up_down <= counter_up_down + 4'd1;
else
 counter_up_down <= counter_up_down - 4'd1;
end 
assign counter = counter_up_down;
endmodule

上下计数器的Verilog测试平台代码:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 up-down counter 与 试验台
// Testbench Verilogcode 对于 up-down counter
module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;

up_down_counter dut(clk, reset,up_down, counter);
initial begin 
clk=0;
对于ever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#200;
up_down=1;
end
endmodule 

上下计数器的仿真波形:

Verilogcode 对于 up-down counter

使用LFSR的随机计数器的Verilog代码:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 random counter using linear shift feedback register
 module random_counter_lfsr(input clk, rst_n,   
                 input[4:0] initialized_value,  
                 output[4:0] counter_random);  
 wire [4:0] counter_lfsr;  
 wire d_xor;  
  xor xor_u(d_xor,counter_lfsr[1],counter_lfsr[4]);  
 D_FF u0(.q(counter_lfsr[0]), .d(counter_lfsr[4]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[0]));  
 D_FF u1(.q(counter_lfsr[1]), .d(counter_lfsr[0]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[1]));  
 D_FF u2(.q(counter_lfsr[2]), .d(d_xor), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[2]));  
 D_FF u3(.q(counter_lfsr[3]), .d(counter_lfsr[2]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[3]));  
 D_FF u4(.q(counter_lfsr[4]), .d(counter_lfsr[3]), .rst_n(rst_n), .clk(clk),.init_value(initialized_value[4])); 
 assign counter_random = counter_lfsr;  
 endmodule    
 // FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 random counter using linear shift feedback register
// Verilogcode 对于 D_FF using in random counter
 module D_FF (q, d, rst_n, clk,init_value);  
 output q;  
 input d, rst_n, clk,init_value;  
 reg q; 
 always @(posedge clk or negedge rst_n)  
 if (~rst_n)  
 q <= init_value;    
 else  
 q <= d; 
 endmodule  

使用LFSR的随机计数器的Verilog测试平台代码:

// FPGA projects using Verilog/ VHDL
// hzgifts.cn: FPGA projects, Verilogprojects, VHDL projects
// Verilogcode 对于 random counter 与 试验台
// Testbench Verilogcode 对于 random counter
module randomcounter_testbench();
reg clk, reset;
reg [4:0] initialized_value;
wire [4:0] counter_random;

random_counter_lfsr dut( clk, reset,   
                 initialized_value,  
                 counter_random);  
initial begin 
clk=0;
对于ever #5 clk=~clk;
end
initial begin
reset=0;
initialized_value=5'b11111;
#20;
reset=1;
end
endmodule 

随机计数器的仿真波形:

使用LFSR的随机计数器的Verilog代码

推荐的 Verilog projects:
2. Verilogcode 对于 FIFO memory
3. 用于16位单周期MIPS处理器的Verilog代码
4. VerilogHDL中的可编程数字延迟计时器
5. 用于数字电路中基本逻辑组件的Verilog代码
6. 用于32位无符号除法器的Verilog代码
7. 用于定点矩阵乘法的Verilog代码
8. VerilogHDL中的车牌许可证识别
9. 提前进位乘法器的Verilog代码
10。 Verilogcode 对于 a Microcontroller
11。 Verilogcode 对于 4x4 Multiplier
12 停车场系统的Verilog代码
13 使用Verilog HDL在FPGA上进行图像处理
14。 如何使用Verilog HDL将文本文件加载到FPGA中
15 交通信号灯控制器的Verilog代码
16。 FPGA上的闹钟的Verilog代码
17。 比较器设计的Verilog代码
18岁 Verilogcode 对于 D Flip Flop
19 Verilogcode 对于 Full Adder
20 带testbench的计数器的Verilog代码
21 16位RISC处理器的Verilog代码
22 用于在FPGA上反跳按钮的Verilog代码
23。 如何为双向/输入端口编写Verilog Testbench
29。 Verilogcode 对于 Multiplexers
30岁  Verilog中的N位加法器设计
31。 Verilogvs VHDL:通过示例解释
32。 FPGA上时钟分频器的Verilog代码
33。 如何在Verilog中生成时钟使能信号
34。 Verilogcode 对于 PWM Generator
35岁 Verilog编码与软件编程
36。 Moore FSM序列检测器的Verilog代码

37。 Basys 3 FPGA上的7段显示控制器的Verilog代码
FPGA VerilogVHDL courses

没意见:

发表评论

热门FPGA项目