根据一些读者的要求,我在此VHDL项目中为FIFO存储器制作了VHDL代码(先进先出存储器的Verilog代码).
的 先进先出 具有16个8位数据宽度级和五个状态信号,包括上溢,下溢,空,满和阈值。通过在Xilinx ISIM上进行混合语言仿真,使用相同的Verilog测试平台代码验证FIFO存储器的VHDL代码。

先进先出的VHDL代码如下:
Library IEEE; USE IEEE.Std_logic_1164.all; -- FPGA projects using VHDL/ VHDL -- fpga4student.com -- 先进先出存储器的VHDL代码 entity fifo_mem is port( data_out : out std_logic_vector(7 downto 0); fifo_full, fifo_empty, fifo_threshold,
fifo_overflow, fifo_underflow: out std_logic; clk :in std_logic; rst_n: in std_logic; wr :in std_logic; rd: in std_logic; data_in: in std_logic_vector(7 downto 0) ); end fifo_mem; architecture Behavioral of fifo_mem is component write_pointer port( wptr : out std_logic_vector(4 downto 0); fifo_we: out std_logic; clk :in std_logic; rst_n: in std_logic; wr :in std_logic; fifo_full: in std_logic ); end component; component read_pointer port( rptr : out std_logic_vector(4 downto 0); fifo_rd: out std_logic; clk :in std_logic; rst_n: in std_logic; rd :in std_logic; fifo_empty: in std_logic ); end component; component memory_array port( data_out : out std_logic_vector(7 downto 0); rptr: in std_logic_vector(4 downto 0); clk :in std_logic; fifo_we: in std_logic; wptr :in std_logic_vector(4 downto 0); data_in: in std_logic_vector(7 downto 0) ); end component; component status_signal port( fifo_full, fifo_empty, fifo_threshold: out std_logic; fifo_overflow, fifo_underflow : out std_logic; wr, rd, fifo_we, fifo_rd,clk,rst_n :in std_logic; wptr, rptr: in std_logic_vector(4 downto 0) ); end component; signal empty, full: std_logic; signal wptr,rptr: std_logic_vector(4 downto 0); signal fifo_we,fifo_rd: std_logic; begin write_pointer_unit: write_pointer port map ( wptr => wptr, fifo_we=> fifo_we, wr=> wr, fifo_full => full, clk => clk, rst_n => rst_n ); read_pointer_unit: read_pointer port map ( rptr => rptr, fifo_rd => fifo_rd, rd => rd , fifo_empty => empty, clk => clk, rst_n => rst_n ); memory_array_unit: memory_array port map ( data_out => data_out, data_in => data_in, clk => clk, fifo_we => fifo_we, wptr => wptr, rptr => rptr ); status_signal_unit: status_signal port map ( fifo_full => full, fifo_empty => empty, fifo_threshold => fifo_threshold, fifo_overflow => fifo_overflow, fifo_underflow => fifo_underflow, wr => wr, rd => rd, fifo_we => fifo_we, fifo_rd => fifo_rd, wptr => wptr, rptr => rptr, clk => clk, rst_n => rst_n ); fifo_empty <= empty; fifo_full <= full; end Behavioral; Library IEEE; USE IEEE.Std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; -- FPGA projects using VHDL/ VHDL -- fpga4student.com -- 先进先出存储器的VHDL代码 -- status signals entity status_signal is port( fifo_full, fifo_empty, fifo_threshold: out std_logic; fifo_overflow, fifo_underflow : out std_logic; wr, rd, fifo_we, fifo_rd,clk,rst_n :in std_logic; wptr, rptr: in std_logic_vector(4 downto 0) ); end status_signal; architecture Behavioral of status_signal is signal fbit_comp, overflow_set, underflow_set: std_logic; signal pointer_equal: std_logic; signal pointer_result:std_logic_vector(4 downto 0); signal full, empty: std_logic; begin fbit_comp <= wptr(4) xor rptr(4); pointer_equal <= '1'
when (wptr(3 downto 0) = rptr(3 downto 0)) else '0'; pointer_result <= wptr - rptr; overflow_set <= full and wr; underflow_set <= empty and rd; full <= fbit_comp and pointer_equal; empty <= (not fbit_comp) and pointer_equal; fifo_threshold <= '1'
when (pointer_result(4) or pointer_result(3))='1' else '0'; fifo_full <= full; fifo_empty <= empty; process(clk,rst_n) begin if(rst_n='0') then fifo_overflow <= '0'; elsif(rising_edge(clk)) then if ((overflow_set='1')and (fifo_rd='0')) then fifo_overflow <='1'; elsif(fifo_rd='1') then fifo_overflow <= '0'; end if; end if; end process; process(clk,rst_n) begin if(rst_n='0') then fifo_underflow <='0'; elsif(rising_edge(clk)) then if((underflow_set='1')and(fifo_we='0')) then fifo_underflow <='1'; elsif(fifo_we='1') then fifo_underflow <='0'; end if; end if; end process; end Behavioral; Library IEEE; USE IEEE.Std_logic_1164.all; USE ieee.numeric_std.ALL; -- FPGA projects using VHDL/ VHDL -- fpga4student.com -- 先进先出存储器的VHDL代码 -- Memory array entity memory_array is port( data_out : out std_logic_vector(7 downto 0); rptr: in std_logic_vector(4 downto 0); clk :in std_logic; fifo_we: in std_logic; wptr :in std_logic_vector(4 downto 0); data_in: in std_logic_vector(7 downto 0) ); end memory_array; architecture Behavioral of memory_array is type mem_array is array (0 to 15) of std_logic_vector(7 downto 0); signal data_out2: mem_array; begin process(clk) begin if(rising_edge(clk)) then if(fifo_we='1') then data_out2(to_integer(unsigned(wptr(3 downto 0)))) <= data_in; end if; end if; end process; data_out <= data_out2(to_integer(unsigned(rptr(3 downto 0)))); end Behavioral; Library IEEE; USE IEEE.Std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; -- FPGA projects using VHDL/ VHDL -- fpga4student.com -- 先进先出存储器的VHDL代码 -- Read pointer entity read_pointer is port( rptr : out std_logic_vector(4 downto 0); fifo_rd: out std_logic; clk :in std_logic; rst_n: in std_logic; rd :in std_logic; fifo_empty: in std_logic ); end read_pointer; architecture Behavioral of read_pointer is signal re: std_logic; signal read_addr:std_logic_vector(4 downto 0); begin rptr <= read_addr; fifo_rd <= re ; re <= (not fifo_empty) and rd; process(clk,rst_n) begin if(rst_n='0') then read_addr <= (others => '0'); elsif(rising_edge(clk)) then if(re='1') then read_addr <= read_addr + "00001"; end if; end if; end process; end Behavioral; Library IEEE; USE IEEE.Std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; -- FPGA projects using VHDL/ VHDL -- fpga4student.com -- 先进先出存储器的VHDL代码 -- Write pointer entity write_pointer is port( wptr : out std_logic_vector(4 downto 0); fifo_we: out std_logic; clk :in std_logic; rst_n: in std_logic; wr :in std_logic; fifo_full: in std_logic ); end write_pointer; architecture Behavioral of write_pointer is signal we: std_logic; signal write_addr:std_logic_vector(4 downto 0); begin fifo_we <= we; we <= (not fifo_full) and wr; wptr <= write_addr; process(clk,rst_n) begin if(rst_n='0') then write_addr <= (others => '0'); elsif(rising_edge(clk)) then if(we='1') then write_addr <= write_addr + "00001"; end if; end if; end process; end Behavioral;
通过使用与以下相同的测试平台代码来验证FIFO存储器的VHDL代码 以前的帖子。我使用Xilinx ISIM来运行混合语言仿真。 先进先出存储器的VHDL代码的Verilog测试平台代码,也可以下载 这里.
运行模拟后,正确的结果应显示如下:110, data_out = 1, mem = 1
120,wr = 1,rd = 0,data_in = 02
130, data_out = 1, mem = 1
140,wr = 0,rd = 0,data_in = 02
150, data_out = 1, mem = 1
170, data_out = 1, mem = 1
190, data_out = 1, mem = 1
190,wr = 1,rd = 0,data_in = 03
210, data_out = 1, mem = 1
210,wr = 0,rd = 0,data_in = 03
230, data_out = 1, mem = 1
250, data_out = 1, mem = 1
260,wr = 1,rd = 0,data_in = 04
270, data_out = 1, mem = 1
280,wr = 0,rd = 0,data_in = 04
290, data_out = 1, mem = 1
310, data_out = 1, mem = 1
330, data_out = 1, mem = 1
330,wr = 1,rd = 0,data_in = 05
350, data_out = 1, mem = 1
350,wr = 0,rd = 0,data_in = 05
370, data_out = 1, mem = 1
390, data_out = 1, mem = 1
400,wr = 1,rd = 0,data_in = 06
410, data_out = 1, mem = 1
420,wr = 0,rd = 0,data_in = 06
430, data_out = 1, mem = 1
450, data_out = 1, mem = 1
470, data_out = 1, mem = 1
470,wr = 1,rd = 0,data_in = 07
490, data_out = 1, mem = 1
490,wr = 0,rd = 0,data_in = 07
510, data_out = 1, mem = 1
530, data_out = 1, mem = 1
540,wr = 1,rd = 0,data_in = 08
550, data_out = 1, mem = 1
560,wr = 0,rd = 0,data_in = 08
570, data_out = 1, mem = 1
590, data_out = 1, mem = 1
610, data_out = 1, mem = 1
610,wr = 1,rd = 0,data_in = 09
630, data_out = 1, mem = 1
630,wr = 0,rd = 0,data_in = 09
650, data_out = 1, mem = 1
670, data_out = 1, mem = 1
680,wr = 1,rd = 0,data_in = 0a
690, data_out = 1, mem = 1
700,wr = 0,rd = 0,data_in = 0a
710, data_out = 1, mem = 1
730, data_out = 1, mem = 1
750, data_out = 1, mem = 1
750,wr = 1,rd = 0,data_in = 0b
770, data_out = 1, mem = 1
770,wr = 0,rd = 0,data_in = 0b
790, data_out = 1, mem = 1
810, data_out = 1, mem = 1
820,wr = 1,rd = 0,data_in = 0c
830, data_out = 1, mem = 1
840,wr = 0,rd = 0,data_in = 0c
850, data_out = 1, mem = 1
870, data_out = 1, mem = 1
890, data_out = 1, mem = 1
890,wr = 1,rd = 0,data_in = 0d
910, data_out = 1, mem = 1
910,wr = 0,rd = 0,data_in = 0d
930, data_out = 1, mem = 1
950, data_out = 1, mem = 1
960,wr = 1,rd = 0,data_in = 0e
970, data_out = 1, mem = 1
980,wr = 0,rd = 0,data_in = 0e
990, data_out = 1, mem = 1
1010, data_out = 1, mem = 1
1030, data_out = 1, mem = 1
1030,wr = 1,rd = 0,data_in = 0f
1050, data_out = 1, mem = 1
1050,wr = 0,rd = 0,data_in = 0f
1070, data_out = 1, mem = 1
1090, data_out = 1, mem = 1
1100,wr = 1,rd = 0,data_in = 10
1110, data_out = 1, mem = 1
1120,wr = 0,rd = 0,data_in = 10
1130, data_out = 1, mem = 1
1150, data_out = 1, mem = 1
1170, data_out = 1, mem = 1
1170,wr = 1,rd = 0,data_in = 11
1190, data_out = 1, mem = 1
1190,wr = 0,rd = 0,data_in = 11
1210, data_out = 1, mem = 1
1220,wr = 0,rd = 1,data_in = 11
1230, data_out = 1, mem = 1
通过------通过----------通过--------------通过
1240,wr = 0,rd = 0,data_in = 11
1250, data_out = 2, mem = 2
1260,wr = 0,rd = 1,data_in = 11
1270, data_out = 2, mem = 2
通过------通过----------通过--------------通过
1280,wr = 0,rd = 0,data_in = 11
1290, data_out = 3, mem = 3
1300,wr = 0,rd = 1,data_in = 11
1310, data_out = 3, mem = 3
通过------通过----------通过--------------通过
1320,wr = 0,rd = 0,data_in = 11
1330, data_out = 4, mem = 4
1340,wr = 0,rd = 1,data_in = 11
1350, data_out = 4, mem = 4
通过------通过----------通过--------------通过
1360,wr = 0,rd = 0,data_in = 11
1370, data_out = 5, mem = 5
1380,wr = 0,rd = 1,data_in = 11
1390, data_out = 5, mem = 5
通过------通过----------通过--------------通过
1400,wr = 0,rd = 0,data_in = 11
1410, data_out = 6, mem = 6
1420,wr = 0,rd = 1,data_in = 11
1430, data_out = 6, mem = 6
通过------通过----------通过--------------通过
1440,wr = 0,rd = 0,data_in = 11
1450, data_out = 7, mem = 7
1460,wr = 0,rd = 1,data_in = 11
1470, data_out = 7, mem = 7
通过------通过----------通过--------------通过
1480,wr = 0,rd = 0,data_in = 11
1490, data_out = 8, mem = 8
1500,wr = 0,rd = 1,data_in = 11
1510, data_out = 8, mem = 8
通过------通过----------通过--------------通过
1520,wr = 0,rd = 0,data_in = 11
1530, data_out = 9, mem = 9
1540,wr = 0,rd = 1,data_in = 11
1550, data_out = 9, mem = 9
通过------通过----------通过--------------通过
1560,wr = 0,rd = 0,data_in = 11
1570, data_out = 10, mem = 10
1580,wr = 0,rd = 1,data_in = 11
1590, data_out = 10, mem = 10
通过------通过----------通过--------------通过
1600,wr = 0,rd = 0,data_in = 11
1610, data_out = 11, mem = 11
1620,wr = 0,rd = 1,data_in = 11
1630, data_out = 11, mem = 11
通过------通过----------通过--------------通过
1640,wr = 0,rd = 0,data_in = 11
1650, data_out = 12, mem = 12
1660,wr = 0,rd = 1,data_in = 11
1670, data_out = 12, mem = 12
通过------通过----------通过--------------通过
1680,wr = 0,rd = 0,data_in = 11
1690, data_out = 13, mem = 13
1700,wr = 0,rd = 1,data_in = 11
1710, data_out = 13, mem = 13
通过------通过----------通过--------------通过
1720,wr = 0,rd = 0,data_in = 11
1730, data_out = 14, mem = 14
1740,wr = 0,rd = 1,data_in = 11
1750, data_out = 14, mem = 14
通过------通过----------通过--------------通过
1760,wr = 0,rd = 0,data_in = 11
1770, data_out = 15, mem = 15
1780年,wr = 0,rd = 1,data_in = 11
1790, data_out = 15, mem = 15
通过------通过----------通过--------------通过
1800,wr = 0,rd = 0,data_in = 11
1810, data_out = 16, mem = 16
1820,wr = 0,rd = 1,data_in = 11
1830, data_out = 16, mem = 16
通过------通过----------通过--------------通过
先进先出存储器的仿真波形:

通过观察仿真波形和存储器,可以很容易地看到如何将数据写入FIFO以及如何从FIFO读取数据。值得注意的是,状态信号(例如上溢,下溢,空,满)对于确定FIFO的正确性至关重要。
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你能帮我吗,我想要fifo 7 * 7和路由器7 * 7的代码
回复删除您能否提供FIFO的硬件设计,以便更好地了解存储器和存储元件
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